Phase detectors, which determine the difference in phase between two signals, are used in a variety of circuits. A common use for phase detectors is in closed loop clock generator circuits, such as phase-lock loops and delay-lock loops. A typical delay-lock loop 10 is shown in FIG. 1. The delay-lock loop 10 includes a phase detector 14 that receives a reference clock signal CLKREF and a feedback clock signal CLKFB. As explained in greater detail below, the CLKFB signal is derived from a signal generated at the output of the delay-lock loop 10. The delay-lock loop 10 delays the CLKREF signal to produce the output signal by a delay that causes the CLKREF and CLKFB signals to have substantially the same phase.
The phase detector 14 compares the phase of the CLKREF signal to the phase of the CLKFB signal and generates one of two output signals indicative of the phase difference. More specifically, when the phase CLKFB signal leads the phase of the CLKREF signal, the phase detector generates an INCR signal on line 16 to increase the phase of the CLKFB signal. The phase of the CLKFB signal is increased by increasing the delay of the CLKREF signal that is used to generate the CLKFB signal. Conversely, when the CLKFB signal lags the CLKREF signal, the phase detector generates a DECR signal on line 18 to decrease the phase of the CLKFB signal. The phase of the CLKFB signal is decreased by decreasing the delay of the CLKREF signal that is used to generate the CLKFB signal.
The DECR and INCR signals from the phase detector 14 are applied to a delay control circuit 20. The delay control circuit 20 generates delay control signals DELCONA-N that are applied to the control inputs of respective delay cells 24A-N. The delay cells 24A-N are coupled in series with each other from a first delay cell 24A to a last delay cell 24N. The first delay cell 24A receives the CLKREF signal and delays it by the number of delay cells 24A-N that are enabled by the respective DELCON signals. If a delay cell 24 is not enabled, it simply passes the signal applied to its input directly to its output without any appreciable delay of the input signal. The final delay cell 24N generates an output clock signal CLKOUT, which is also used as the CLKFB signal.
In operation, any difference in the phases of the CLKREF and CLKFB signals causes the phase detector 14 to output either a DECR or INCR signal that caused the delay control circuit 20 to alter the number of delay cells 24 that are enabled and hence the delay of the CLKOUT signal relative to the CLKREF signal. More specifically, if the CLKFB signal lags the CLKREF signal, the phase detector 14 generates a DECR signal to reduce the number of enabled delay cells 24, thereby decreasing the phase of the CLKFB signal. Conversely, if the CLKFB signal leads the CLKREF signal, the phase detector 14 generates an INCR signal to increase the number of enabled delay cells 24, thereby increasing the phase of the CLKFB signal.
Although the CLKFB signal is shown in FIG. 1 as being the same as the CLKOUT signal, in practice the CLKFB signal is often taken from a clock tree through which the CLKOUT is coupled. For example, as explained in greater below, the CLKOUT signal may be coupled to an output latch (not shown) of a memory device. The output latch couples a data signal to an externally accessible terminal responsive to a transition of the CLKOUT signal. However, the CLKOUT signal may be delayed as it is coupled to the output latch. By using the clock input of the data latch as the circuit node at which the CLKFB signal is derived, the coupling of data signals to the externally accessible terminal can be synchronized to an externally received CLKREF signal.
In another type of delay-lock loop, the DELCON signal generated by the delay control circuit 20 is an analog signal or a set of digital signals that controls the magnitude delay of each of the delay cells 24A-N rather than the number of delay cells 24A-N that are enabled. The delay of each of the delay cells 24A-N is typically incrementally increased or decreased responsive to the respective INCR or DECR signals generated by the phase detector 14.
Another closed loop clock generator circuit that uses a phase detector is a phase-lock loop. A typical phase-lock loop 30 is shown in FIG. 2. The phase-lock loop 30 includes the phase detector 14 used in the delay-lock loop of FIG. 1, and it operates on CLKREF and CLKFB signals in the same manner as described above. The INCR and DECR signals from the phase detector 14 are coupled to a frequency control circuit 34 that generates a frequency control signal FREQCON, which may be either an analog signal or a set of digital signals. The FREQCON signal is applied to a control input of a voltage-controlled oscillator 38, which generates an output clock signal CLKOUT having a frequency that is determined by the magnitude of the FREQCON signal. The CLKOUT signal is again used as the CLKFB signal that is applied to the phase detector 14.
In operation, any difference in the phases of the CLKREF and CLKFB signals causes the phase detector 14 to output either an INCR or DECR signal that caused the frequency control circuit 34 to alter the frequency of the CLKOUT signal generated by the voltage-controlled oscillator 38. If the CLKFB signal lags the CLKREF signal, the phase detector 14 generates a DECR signal to cause the voltage-controlled oscillator 38 to decrease the period of the CLKFB signal. As a result, the phase of the CLKFB signal is increased so that it's phase is closer to the phase of the CLKREF signal. Conversely, If the CLKFB signal leads the CLKREF signal, the phase detector 14 generates an INCR signal to cause the voltage-controlled oscillator 38 to increase the period of the CLKFB signal. As a result, the phase of the CLKFB signal decreases to be closer to the phase of the CLKREF signal.
Typical phase-lock loops often include components in addition to the phase detector 14 and voltage-controlled oscillator 38, such as a loop amplifier (not shown) to increase the gain of the feedback loop, and a loop filter (not shown) to filter out any high frequency components in the signal controlling the voltage-controlled oscillator 38 and to control the dynamics of the loop.
A typical phase detector 40 that may be used in a delay-lock loop or phase-lock loop, including the delay-lock loop 10 of FIG. 1 and the phase-lock loop 30 of FIG. 2 is shown in FIG. 3. The phase detector 40 includes a first NAND gate 42 that receives the CLKREF signal, and a second NAND gate 44 that receives the CLKFB signal. Both of these NAND gates 42, 44 are enabled by their other inputs being coupled to a supply voltage VCC. The output of each of the NAND gates 42, 44 is coupled to an input of a respective NAND gate 46, 48 through respective inverters 50, 52. The NAND gates 46, 48 are coupled to each other to form a flip-flop 56, which is reset by a low applied to the inputs of both NAND gate 48 and NAND gate 46 and set by the first high-going transition applied to the inputs of the NAND gates 48 and 46. As explained below, the flip-flop 56 functions as a comparator to compare the phase of the CLKREF signal to the phase of the CLKFB signal.
The outputs of the flip-flop 56 are coupled to an output circuit 60 that functions as a signal generator to generate either the INCR signal or the DECR signal. As explained in greater detail below, the output circuit 60 generates an active high INCR signal when the output of the NAND gate 48 transitions low. Similarly, the output circuit 60 also generates an active high DECR signal when the output of the NAND gate 46 transitions low. The output circuit 60 includes a first PMOS transistor 62 and a first NMOS transistor 64 coupled in series between the output of the NAND gate 46 and ground. The gates of the transistors 62, 64 are coupled to the output of the NAND gate 48, the input of INV gate 102 is coupled to the drains of the transistors 62, 64. The output circuit also includes a second PMOS transistor 66 and a second NMOS transistor 68 coupled in series between the output of the NAND gate 48 and ground. The gates of the transistors 66, 68 are coupled to the output of the NAND gate 46, and the input of INV gate 124 is coupled to the drains of the transistors 66, 68.
When the output of the NAND gate 48 is low, the output of the NAND gate 46 will be high. The low at the output of the NAND gate 48 turns ON the PMOS transistor 62 and turns OFF the NMOS transistor 64, thereby coupling the high at the output of the NAND gate 46 to the input of INV gate 102. At the same time, the high at the output of the NAND gate 46 turns ON the NMOS transistor 68 to hold the input to INV gate 124 low. In the same manner, when the output of the NAND gate 46 is low, the output of the NAND gate 48 will be high. The low at the output of the NAND gate 46 turns ON the PMOS transistor 66 and turns OFF the NMOS transistor 68, thereby coupling the high at the output of the NAND gate 48 to the input of INV gate 124. The high at the output of the NAND gate 48 also turns ON the NMOS transistor 64 to hold the input to INV gate 102 low. During reset, when both of the NAND gates 46, 48 simultaneously receive a low at their respective inputs, the outputs of both NAND gates 46, 48 will be high. In such case, the high at the output of the NAND gate 46 will turn OFF the PMOS transistor 66 and turn ON the NMOS transistor 68, thereby holding the input of INV gate 124 low. Similarly, the high at the output of the NAND gate 48 will turn OFF the PMOS transistor 62 and turn ON the NMOS transistor 64, thereby holding the inut of INV gate 102 low.
The signal E is coupled through a pair of inverters 96, 98 to a NAND gate 100. The NAND gate 100 also receives the CLKREF signal after being coupled through a pair of inverters 106, 108, and the CLKFB signal after being coupled through a pair of inverters 110, 112. In a similar manner, the signal F is coupled through a pair of inverters 116, 118 to a second NAND gate 120. The NAND gate 120 also receives the CLKREF signal coupled through the inverters 104, 108, and it also receives the CLKFB signal coupled through the inverters 110, 112.
The overall operation of the phase detector 40 will now be explained with reference to the timing diagrams shown in FIGS. 4 and 5 in which the signals “A”-“D” are present at the correspondingly marked nodes of the phase detector 40 as shown in FIG. 3, “A” is the CLKREF signal, and “B” is the CLKFB signal. With reference, first, to FIG. 4 in which the CLKFB signal lags the CLKREF signal, just prior to time t0, both “A” and “B” are low, thereby making both “C” and “D” high. As a result, the output circuit 60 holds both E and F low. At time t0, “A” transitions high so that the NAND gate 46 receives that high as well as the high “D” signal, thereby causing the signal “C” at the output of the NAND gate 46 to transition low. The low “C” signal causes the “D” signal at the output of the NAND gate 48 to remain high after t1 when the signal “B” transitions high. The low “C” signal causes the output circuit 60 to couple the high at the output of the NAND gate 48 to line 18 to generate an active high F signal while the E signal is low. The NAND gate 100 will cause the INCR signal to be active high only if all of its inputs are high. However, as is apparent from FIG. 4, there is no time where the signal E, CLKREF, and CLKFB are all high. Therefore, the INCR signal remains inactive low. Signal F is applied to the NAND gate 120 along with the CLKREF and CLKFB signals. From FIG. 4 it can be seen that the signals F, CLKREF, and CLKFB are all high for a period of time, thereby causing the DECR signal to go high. Therefore, when the CLKREF signal leads the CLKFB signal a DECR signal is generated. At time t2, the signal “A” transitions low, thereby causing the signal “C” at the output of the NAND gate 46 to transition high. The NAND gate 48 then receives the high “B” signal and the high “C” signal, so that the “D” signal at the output of the NAND gate 48 transitions low. The low “D” signal causes the output circuit 60 to couple the high “C” signal to line 16, thereby producing an active high E signal. The high “C” signal as well as the low “D” signal cause the F signal to remain low during this time. However, since CLKREF, and CLKFB are not both high, the outputs of NAND 100 and NAND 120 are held high, resulting in DECR and INCR being held low during this period. At t3, the “B” signal transitions low, thereby causing the “D” signal to transition high. Since the low “A” signal also causes the “C” signal to be high, the output circuit 60 holds both the E and F signals low, and hence the INCR and DECR signals are both low. At time t4, the operation repeats the operation explained above starting at time t0.
The operation of the phase detector 40 for the CLKFB signal leading the CLKREF signal will now be explained with reference to FIG. 5. Just prior to time t0, both “A” and “B” are low, thereby making both “C” and “D” high. As a result, the output circuit 60 holds both E and F low. At time t0, signal “B” transitions high so that the NAND gate 48 receives that high as well as the high “C” signal, thereby causing the signal “D” at the output of the NAND gate 48 to transition low. The low “D” signal causes the “C” signal at the output of the NAND gate 46 to remain high after t1 when the signal “A” transitions high. The low “D” signal causes the output circuit 60 to couple the high at the output of the NAND gate 46 to line 16 to generate an active high E signal while the F signal is held low. The NAND gate 120 will cause the DECR signal to be active high only if all of its inputs are high. However, as is apparent from FIG. 5, there is no time where the signals “F”, CLKREF, and CLKFB are all high at the same time. Therefore, the DECR signal remains inactive low. Similarly, the signal “E” is applied to the NAND gate 100 along with the CLKREF and CLKFB signals. From FIG. 5 it can be seen that the signals “E”, CLKREF, and CLKFB are all high for a period of time, thereby causing the INCR signal to go high. Therefore, when the CLKFB signal leads the CLKREF signal, an INCR signal is generated. At time t2, the signal “B” transitions low, thereby causing the signal “D” at the output of the NAND gate 48 to transition high. The NAND gate 46 then receives the high “A” signal and the high “D” signal, so that the “C” signal at the output of the NAND gate 46 transitions low. The low “C” signal causes the output circuit 60 to couple the high “D” signal to line 18, thereby producing an active high F signal. The high “D” signal as well as the low “C” signal cause the E signal to remain low during this time. However, since CLKREF and CLKFB are not both high, the outputs of NAND gate 120 and NAND gate 100 are held high, resulting in DECR and INCR being held low during this period. At t3, the “A” signal transitions low, thereby causing the “C” signal to transition high. Since the low “B” signal also causes the “D” signal to be high, the output circuit 60 holds both the E and F signals low, and hence the INCR and DECR signals are both held low. At time t4, the operation repeats the operation explained above starting at time t0.
Comparing FIGS. 4 and 5, it can be seen that, when the CLKFB signal lags the CLKREF signal as shown in FIG. 4, the DECR signal is active high. As a result, the phase of the CLKFB signal will be decreased toward the phase of the phase of the CLKREF signal. When the CLKFB signal leads the CLKREF signal as shown in FIG. 4, the INCR signal is active high. As a result, the phase of the CLKFB signal will be increased toward the phase of the phase of the CLKREF signal.
Although the phase detector 40 can provide adequate control of the phase of the CLK signal in many instances, it has the sometimes serious disadvantage of producing a great deal of “phase jitter.” Phase jitter is a term referring to high frequency variations in the phase of a periodic signal, such as the CLKOUT signal produced by a closed-loop clock generator circuit. Phase jitter can have several different causes. For example, in a phase-lock loop phase jitter can result from high frequency components in an error signal that is produced by a phase detector and not adequately attenuated by a loop filter. Phase jitter can be produced in the delay lock loop 10 of FIG. 1 and in the phase-lock loop 30 of FIG. 2, as well as in similar closed-loop circuits, because of the characteristics of the phase detector 14 used in those circuits, such as the phase detector 40 shown in FIG. 3.
The phase detector 40 will produce phase jitter any time the increase or decrease in the phase of the CLKOUT signal resulting from the INCR or DECR signal, respectively, is greater than the phase difference between the CLKREF and CLKFB signal that resulted in the INCR or DECR signal being generated. From the point of view of time delays rather than phase differences, clock jitter will occur any time the increase or decrease in the delay of the CLKOUT signal resulting from the INCR or DECR signal, respectively, is greater than the difference in time between a transition of the CLKREF and a corresponding transition of the CLKFB signal that resulted in the INCR or DECR signal being generated. For example, if the CLKFB signal lags CLKREF the signal by 25 picoseconds (“ps”), the phase detector 14 will produce an DECR signal to reduce the phase or delay time of the CLKFB signal. If the minimum increment in the delay time of the delay-lock loop 10 or phase-lock loop 30 is 50 ps, the DECR signal will cause the timing of the CLKOUT signal to be reduced by 50 ps. On the next transition of the CLKREF signal, the CLKFB signal will now lead the CLKREF signal by 25 ps (i.e., the original 25 ps lead minus the 50 ps adjustment). As a result, the phase detector 14 will produce an INCR signal, which will cause the timing of the CLKFB signal to be increased by 50 ps thereby causing the CLKFB to again lag the CLKREF signal by 25 ps. The phase or timing of the CLKOUT and CLKFB signals will continue to jump back and forth by 50 ps in this manner. This type of phase jitter will occur with any “arbiter” phase detector that, like the phase detector 14, produces an output signal based on whether the CLKREF signal leads or lags the CLKFB signal. The phase jitter that is present on the CLKOUT signal can greatly reduce the ability of the CLKOUT signal to be used for various purposes. For example, using the CLKOUT signal to clock read data signals out of a memory device will cause the read data signals to have a great deal of phase jitter, thereby making it more difficult to capture the read data signals at a memory controller or other device. This problem can be particularly severe at higher clock speeds where the period of time that data signals are valid becomes increasingly small.
There is therefore a need for a phase detector that can be used in a closed-loop clock generating circuit that does not inherently cause the closed-loop clock generating circuit to produce a CLKOUT signal having continuous phase jitter.